One of the major issues in the development of semiconductor memory devices is to maximize data storage density, i.e., the number of bits of data that can be stored per unit area. Thus, generally it is desired to develop memory chips having the smallest possible physical size, while storing a maximum amount of data. This has led to the development of memory chips that can store multiple bits of data in a single memory cell, also referred to as multilevel memory chips.
In conventional single bit per cell memory devices, the memory cell assumes one of two information storage states, either an on-state or an off-state. This combination of either on or off defines one bit of information. In bilevel memories, since the cells can only have two different values of threshold voltage, Vt, during the reading operation, it is only necessary to sense whether or not the addressed transistor is conductive. This is generally done by comparing the current flowing through the memory transistor biased with predetermined drain-to-source and gate-to-source voltages with that of a reference transistor under the same bias conditions, either directly through current-mode sensing or after a current-to-voltage conversion through voltage-mode sensing.
Programming and sensing schemes for multilevel memory devices are more complex, typically requiring 2n−1 voltage references, where n is the number of bits stored in the cell. In multilevel flash memories, program operations are very critical. Allocating 4 (2 bits per cell) or more threshold levels within a defined Vt window reduces the available error range. Read operations are more complicated, and it's very important to have an optimal control on program operations to obtain prefixed threshold voltage.
In programming a typical flash memory cell, a potential (such as, for example, approximately 3–12 volts) is applied to the control gate of the cell, the source terminal is grounded, and the drain terminal is connected to a voltage of about 5 volts. This operation can be performed in an array by selectively applying the pulse to the word line which connects the control gates, and biasing the bit line which connects the drains. This is commonly known in the art as the hot electron injection method of programming flash memory cells. Hot electron injection is used to move charge in the floating gate, thus changing the threshold voltage of the floating gate transistor. By placing the high voltage on the control gate, this generates electrons to flow in the channel and some hot electrons are injected on to the floating gate and change the potential of the floating gate to be more negative. Therefore, injection tends to saturate and the threshold voltage of a floating gate transistor follows the same trend. The state of the memory cell transistor is read or sensed by placing an operating voltage (for example, approximately 4–6 volts) on its control gate and 0.5–1 volts on the drain, and then detecting the level of current flowing between the source and drain to determine which memory state the cell is in.
One of the main difficulties in implementing multilevel nonvolatile memory cells is being able to accurately program the cell, i.e. to place just the amount of charge on the floating gate of the cell transistor that is required to obtain the target value of the threshold voltage. The usual manner that is used in the prior art to deal with the problem of accurate charge placement is by using a cell-by-cell program and verify approach. In the program and verify approach, the programming operation is divided into a number of partial steps and the cell is sensed after every step to determine whether or not the target threshold voltage is achieved, so as to continue the programming if this is not the case. As each cell is independently controlled during programming, this technique allows simultaneous programming of a whole byte or even a number of bytes. This procedure ensures that the target Vt is reached, with the accuracy allowed by the quantization inherent in the use of finite programming steps. However, this process can be very long and must be controlled by on-chip logic circuitry.
Further, when using a program and verify algorithm to obtain the target Vt in the programmed cells and a gate voltage ramp programming to shift the threshold cells, it is critical to have a constant Vd (drain voltage) between different program pulses. Vd variations during program operations involve an uncontrolled threshold voltage in the memory cells. These unforeseeable Vt values will cause many problems in successive read operations.
Typically, in a multilevel flash memory, the Vd program voltage value is greater than the Vdd value. To obtain the right program value when starting from a low external voltage supply, a charge pump is necessary. The output of the charge pump will be switched to the drain during program operations, and control of the Vd program value (i.e., the output pump) is necessary.
Using gate voltage ramp programming, the program Vd value seen by programmed cells must be the same, independent of: the temperature, the number of cells to be programmed, Vdd voltage, program current per cell, etc. Some methods used to reduce the pump output variations include using pump-phase stopping, using a single serial regulator, or using a distributed serial cascode regulator. FIG. 1 illustrates a circuit schematic 100 of a single serial regulator approach, while FIG. 2 illustrates a circuit schematic 200 of a distributed serial cascode regulator approach.
While these methods reduce the pump output variations, they have disadvantages. In particular, the single serial regulator approach 100 reduces the final error regulator but is slow, because a big MOS (with a big gate capacitance) is necessary to supply all the current requested by the memory cells 102 to be programmed. Moreover, while the distributed serial regulator 200 is independent of the number of cells 202 being simultaneously programmed, it is not able to correct the error made by the parasitic resistance of Vd program voltage path (composed by the MOS switches 204). The distributed cascode regulator is faster, because the Vreg voltage is stable and constant in time. However, it is not able to compensate for temperature variations. The final Vd regulated is Vreg-Vtcascode (where Vtcascode is the threshold voltage of the local cascode regulator used), and it is temperature dependent by Vtcascode.
Accordingly, a need exists for a more reliable approach to regulating the program voltage for multilevel memory devices during programming. The present invention addresses such as need.